ColdFire Core
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
3-5
Preliminary
the hardware uses one 32-bit register as the active A7 and the other as OTHER_A7. Thus, the register
contents are a function of the processor operation mode, as shown in the following:
if SR[S] = 1
then
A7 = Supervisor Stack Pointer
OTHER_A7 = User Stack Pointer
else
A7 = User Stack Pointer
OTHER_A7 = Supervisor Stack Pointer
The BDM programming model supports direct reads and writes to A7 and OTHER_A7. It is the
responsibility of the external development system to determine, based on the setting of SR[S], the mapping
of A7 and OTHER_A7 to the two program-visible definitions (SSP and USP).
To support dual stack pointers, the following two supervisor instructions are included in the ColdFire
instruction set architecture to load/store the USP:
move.l Ay, USP; move to USP
move.l USP, Ax; move from USP
These instructions are described in the
ColdFire Family Programmer’s Reference Manual
.
NOTE
The USP must be initialized using the
move.l Ay,USP
instruction before any
entry into user mode.
The SSP is loaded during reset exception processing with the contents of
location 0x0000_0000.
Figure 3-4. Stack Pointer Registers (A7 and OTHER_A7)
3.2.4
Condition Code Register (CCR)
The CCR is the LSB of the processor status register (SR). Bits 4–0 act as indicator flags for results
generated by processor operations. The extend bit (X) is also used as an input operand during
multiprecision arithmetic computations. The CCR register must be explicitly loaded after reset and before
any compare (CMP), Bcc, or Scc instructions are executed.
BDM: Load: 0x08F (A7)
Store: 0x18F (A7)
0x800 (OTHER_A7)
Access: A7: User or BDM read/write
OTHER_A7: Supervisor or BDM read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
Address
W
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
