ColdFire Core
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
3-6
Freescale Semiconductor
Preliminary
3.2.5
Program Counter (PC)
The PC contains the currently executing instruction address. During instruction execution and exception
processing, the processor automatically increments contents of the PC or places a new value in the PC, as
appropriate. The PC is a base address for PC-relative operand addressing.
The PC is initially loaded during reset exception processing with the contents of location 0x0000_0004.
Figure 3-6. Program Counter Register (PC)
3.2.6
Vector Base Register (VBR)
The VBR contains the base address of the exception vector table in memory. To access the vector table,
the displacement of an exception vector is added to the value in VBR. The lower 20 bits of the VBR are
BDM: LSB of Status Register (SR)
Access: User read/write
BDM read/write
7
6
5
4
3
2
1
0
R
0
0
0
X
N
Z
V
C
W
Reset:
0
0
0
—
—
—
—
—
Figure 3-5. Condition Code Register (CCR)
Table 3-2. CCR Field Descriptions
Field
Description
7–5
Reserved, must be cleared.
4
X
Extend condition code bit. Set to the C-bit value for arithmetic operations; otherwise not affected or set to a specified
result.
3
N
Negative condition code bit. Set if most significant bit of the result is set; otherwise cleared.
2
Z
Zero condition code bit. Set if result equals zero; otherwise cleared.
1
V
Overflow condition code bit. Set if an arithmetic overflow occurs implying the result cannot be represented in operand
size; otherwise cleared.
0
C
Carry condition code bit. Set if a carry out of the operand msb occurs for an addition, or if a borrow occurs in a
subtraction; otherwise cleared.
BDM: 0x80F (PC)
Access: User read/write
BDM read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
Address
W
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
