ColdFire Core
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
3-7
Preliminary
not implemented by ColdFire processors; they are assumed to be zero, forcing the table to be aligned on a
1 MByte boundary.
Figure 3-7. Vector Base Register (VBR)
3.2.7
Status Register (SR)
The SR stores the processor status and includes the CCR, the interrupt priority mask, and other control
bits. In supervisor mode, software can access the entire SR. In user mode, only the lower 8 bits are
accessible (CCR). The control bits indicate the following states for the processor: trace mode (T bit),
supervisor or user mode (S bit), and master or interrupt state (M bit). All defined bits in the SR have
read/write access when in supervisor mode. The SR register (actually the CCR) must be loaded explicitly
after reset and before any compare (CMP), Bcc, or Scc instructions execute.
BDM: 0x801 (VBR)
Access: Supervisor read/write
BDM read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
Base Address
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BDM: 0x80E (SR)
Access: Supervisor read/write
BDM read/write
System Byte
Condition Code Register (CCR)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
T
0
S
M
0
I
0
0
0
X
N
Z
V
C
W
Reset
0
0
1
0
0
1
1
1
0
0
0
—
—
—
—
—
Figure 3-8. Status Register (SR)
Table 3-3. SR Field Descriptions
Field
Description
15
T
Trace enable. When set, the processor performs a trace exception after every instruction.
14
Reserved, must be cleared.
13
S
Supervisor/user state.
0 User mode
1 Supervisor mode
12
M
Master/interrupt state. Bit is cleared by an interrupt exception and software can set it during execution of the RTE or
move to SR instructions.
11
Reserved, must be cleared.
