Debug Module
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
27-41
Preliminary
When debug interrupt operations complete, the RTE instruction executes and the processor exits emulator
mode. After the debug interrupt handler completes execution, the external development system can use
BDM commands to read the reserved memory locations.
In revision B/B+, the hardware inhibits generation of another debug interrupt during the first instruction
after the RTE exits emulator mode. This behavior is consistent with the logic involving trace mode where
the first instruction executes before another trace exception is generated. Thus, all hardware breakpoints
are disabled until the first instruction after the RTE completes execution, regardless of the programmed
trigger response.
27.6.1.1
Emulator Mode
Emulator mode facilitates non-intrusive emulator functionality. This mode can be entered in three different
ways:
•
Setting CSR[EMU] forces the processor into emulator mode. EMU is examined only if RSTI is
negated and the processor begins reset exception processing. It can be set while the processor is
halted before reset exception processing begins. See
.
•
A debug interrupt always puts the processor in emulation mode when debug interrupt exception
processing begins.
•
Setting CSR[TRC] forces the processor into emulation mode when trace exception processing
begins.
While operating in emulation mode, the processor exhibits the following properties:
•
All interrupts are ignored, including level-7 interrupts.
•
If CSR[MAP] equals 1, all caching of memory and the SRAM module are disabled. All memory
accesses are forced into a specially mapped address space signaled by TT equals 0x2,
TM equals 0x5, or 0x6. This includes stack frame writes and vector fetch for the exception that
forced entry into this mode.
The RTE instruction exits emulation mode. The processor status output port provides a unique encoding
for emulator mode entry (0xD) and exit (0x7).
27.6.2
Concurrent BDM and Processor Operation
The debug module supports concurrent operation of the processor and most BDM commands. BDM
commands may be executed while the processor is running, except these following operations that access
processor/memory registers:
•
Read/write address and data registers
•
Read/write control registers
For BDM commands that access memory, the debug module requests the processor’s local bus. The
processor responds by stalling the instruction fetch pipeline and waiting for current bus activity to
complete before freeing the local bus for the debug module to perform its access. After the debug module
bus cycle, the processor reclaims the bus.
