ColdFire Core
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
3-9
Preliminary
Figure 3-9. Version 2 ColdFire Processor Instruction Fetch Pipeline Diagram
Figure 3-10. Version 2 ColdFire Processor Operand Execution Pipeline Diagram
The instruction fetch pipeline prefetches instructions from local memory using a two-stage structure. For
sequential prefetches, the next instruction address is generated by adding four to the last prefetch address.
This function is performed during the IAG stage and the resulting prefetch address gated onto the core bus
(if there are no pending operand memory accesses which are assigned a higher priority). After the prefetch
address is driven onto the core bus, the instruction fetch cycle accesses the appropriate local memory and
returns the instruction read data back to the IFP during the cycle. If the accessed data is not present in a
local memory (e.g., an instruction cache miss, or an external access cycle is required), the IFP is stalled in
IAG
IC
IB
Core Bus
Address
Core Bus
Read Data
Opword
Extension 1
Extension 2
FIFO
IB
Instruction Fetch Pipeline
+4
Operand Execution Pipeline
DSOC
AGEX
Opword
Extension 1
Extension 2
Core Bus
Read Data
Core Bus
Address
Core Bus
Write
RGF
Data
