Clock Module
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
6-6
Freescale Semiconductor
Preliminary
•
FRCRSTOUT bit in the reset control status register (RCR); see
Section 10.5.1, “Reset Control
6.7
Memory Map and Registers
The clock module programming model shown in
consists of registers that define clock operation
and status as well as additional peripheral power management registers.
6.7.1
Register Descriptions
This subsection provides a description of the clock module registers.
Table 6-4. Clock Module Memory Map
IPSBAR
Offset
1
1
Addresses not assigned to a register and undefined register bits are reserved for expansion.
Register
Width
(bits)
Access
Reset Value
Section/Page
Supervisor Mode Access Only
0x12_0000
Synthesizer Control Register (SYNCR)
16
R/W
0x1002
0x12_0002
Synthesizer Status Register (SYNSR)
8
R
0x00
0x12_0004
Relaxation Oscillator Control Register (ROCR)
16
R/W
See note
2
2
The reset value for ROCR is loaded during reset from the flash information row (bits [9:0]). The bits reset to 0b10_0000_0000
during Power-On Reset.
0x12_0007
Low Power Divider Register (LPDR)
8
R/W
0x00
0x12_0008
Clock Control High Register (CCHR)
8
R/W
0x00
0x12_0009
Clock Control Low Register (CCLR)
8
R/W
See note
3
3
CCLR reset state determined during reset configuration.
0x12_000A
Oscillator Control High Register (OCHR)
8
R/W
See note
4
4
OCHR reset state determined during reset configuration.
0x12_000B
Oscillator Control Low Register (OCLR)
8
R/W
See note
5
5
OCLR reset state determined during reset configuration.
0x12_0012
Real Time Clock Control Register (RTCCR)
8
R/W
0x00
0x12_0013
Backup Watchdog Timer Control Register (BWCR)
8
R/W
0x00
6
6
The contents of BWCR are reset only during Power-On Reset; they are preserved during a warm reset.
0x000C
Peripheral Power Management Register High (PPMRH)
7
7
See
Section 8.2.1, “Peripheral Power Management Registers (PPMRH, PPMRL).”
32
R/W
0x00
0x0018
Peripheral Power Management Register Low (PPMRL)
32
R/W
0x01
