Power Management
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
9-8
Freescale Semiconductor
9.2.4
Peripheral Power Management Clear Register (PPMRC)
The PPMRC register provides a simple memory-mapped mechanism to clear a given bit in the PPMR
x
registers to
enable the clock
for a given IPS module without the need to perform a read-modify-write on
the PPMR
x
. The data value on a register write causes the corresponding bit in the PPMR
x
register to be
cleared. A data value of 64 to 127 provides a global clear function, forcing the entire contents of the
PPMR
x
to be zeroed, enabling all IPS module clocks. In the event on simultaneous writes of the PPMRS
and PPMRC, the write to the PPMRC takes priority. Reads of this register return all zeroes. See
and
9.2.4.1
Low-Power Control Register (LPCR)
The LPCR controls chip operation and module operation during low-power modes. The low-power control
register (LPCR) specifies the low-power mode entered when the STOP instruction is issued, and controls
clock activity in this low-power mode.
Table 9-6. PPMRS Field Descriptions
Field
Description
7
Reserved, should be cleared.
6–0
PPMRS
Set Module Clock Disable
0–63 Set corresponding bit in PPMRx, disabling the module clock
64–127 Set all bits in PPMRx, disabling all the module clocks
IPSBAR
Offset:
0x00_0022 (PPMRC)
Access: write-only
7
6
5
4
3
2
1
0
R
0
W
PPMRC
Reset:
0
0
0
0
0
0
0
0
Figure 9-5. Peripheral Power Management Clear Register (PPMRC)
Table 9-7. PPMRC Field Descriptions
Field
Description
7
Reserved, should be cleared.
6–0
PPMRC
Clear Module Clock Disable
0–63 Clear corresponding bit in PPMRx, enabling the module clock
64–127 Clear all bits in PPMRx, enabling all the module clocks
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
