Overview
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
1-10
Freescale Semiconductor
data, and branch target addresses defining processor activity at the CPU’s clock rate. The MCF52235
includes a new debug signal, ALLPST. This signal is the logical AND of the processor status (PST[3:0])
signals and is useful for detecting when the processor is in a halted state (PST[3:0] = 1111).
The full debug/trace interface is available only on the 112 and 121-pin packages. However, every product
features the dedicated debug serial communication channel (DSI, DSO, DSCLK) and the ALLPST signal.
1.4.3
JTAG
The MCF52235 supports circuit board test strategies based on the Test Technology Committee of IEEE
and the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting of a
16-state controller, an instruction register, and three test registers (a 1-bit bypass register, a 256-bit
boundary-scan register, and a 32-bit ID register). The boundary scan register links the device’s pins into
one shift register. Test logic, implemented using static logic design, is independent of the device system
logic.
The MCF52235 implementation can do the following:
•
Perform boundary-scan operations to test circuit board electrical continuity
•
Sample
MCF52235 system
pins
during
operation and transparently shift out the result
in the
boundary scan register
•
Bypass the MCF52235 for a given circuit board test by effectively reducing the
boundary-scan
register to a single bit
•
Disable the output drive to pins during circuit-board testing
•
Drive output pins to stable levels
1.4.4
On-Chip Memories
1.4.4.1
SRAM
The dual-ported SRAM module provides a general-purpose 16- or 32-Kbyte memory block that the
ColdFire core can access in a single cycle. The location of the memory block can be set to any 16- or
32-Kbyte boundary within the 4-Gbyte address space. This memory is ideal for storing critical code or data
structures and for use as the system stack. Because the SRAM module is physically connected to the
processor's high-speed local bus, it can quickly service core-initiated accesses or memory-referencing
commands from the debug module.
The SRAM module is also accessible by the DMA. The dual-ported nature of the SRAM makes it ideal
for implementing applications with double-buffer schemes, where the processor and a DMA device
operate in alternate regions of the SRAM to maximize system performance.
1.4.4.2
Flash
The ColdFire flash module (CFM) is a non-volatile memory (NVM) module that connects to the
processor’s high-speed local bus. The CFM is constructed with four banks of 32 K
×
16-bit flash arrays to
generate 256 Kbytes of 32-bit flash memory. These arrays serve as electrically erasable and
programmable, non-volatile program and data memory. The flash memory is ideal for program and data
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
