System Control Module (SCM)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
13-17
NOTE
The access control for modules with memory space protected by
PACR0–PACR9 are determined by the PACR0–PACR9 settings. The access
control is not affected by GPACR0, even though the modules are mapped in
its 64-Mbyte address space.
At reset, these on-chip modules are configured to have only supervisor read/write access capabilities. Bit
encodings for the ACCESS_CTRL field in the GPACR are shown in
shows the
memory space protected by the GPACRs and the modules mapped to these spaces.
IPSBAR
Offsets:
0x0030 (GPACR0)
0x0031 (GPACR1)
Access: read/write
7
6
5
4
3
2
1
0
R
LOCK
0
0
0
ACCESS_CTRL
W
Reset:
0
0
0
0
0
0
0
0
Figure 13-10. GPACR Register
Table 13-12. Grouped Peripheral Access Control Register (GPACR) Field Descriptions
Field
Description
7
LOCK
This bit, after set, prevents subsequent writes to the GPACR. Any attempted write to the GPACR generates
an error termination and the contents of the register are not affected. Only a system reset clears this flag.
6–4
Reserved, should be cleared.
3–0
ACCESS_CTRL
This 4-bit field defines the access control for the given memory region.
The encodings for this field are shown in
.
Table 13-13. GPACR ACCESS_CTRL Bit Encodings
Bits
Supervisor Mode
User Mode
0000
Read / Write
No Access
0001
Read
No Access
0010
Read
Read
0011
Read
No Access
0100
Read / Write
Read / Write
0101
Read / Write
Read
0110
Read / Write
Read / Write
0111
No Access
No Access
1000
Read / Write / Execute
No Access
1001
Read / Execute
No Access
1010
Read / Execute
Read / Execute
1011
Execute
No Access
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
