Interrupt Controller Module
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
15-7
Freescale Semiconductor
15.3.2
Interrupt Mask Registers (IMRHn, IMRLn)
The IMRH
n
and IMRL
n
registers are each 32 bits and provide a bit map for each interrupt to allow the
request to be disabled (1 = disable the request, 0 = enable the request). The IMR
n
is set to all ones by reset,
disabling all interrupt requests. The IMR
n
can be read and written. A write that sets bit 0 of the IMRL
n
forces the other 63 bits to be set, disabling all interrupt sources, and providing a global mask-all capability.
IPSBAR
Offset:
0x00_0C08 (IMRH0)
0x00_0D08 (IMRH1)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
INT_MASK[63:32]
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Figure 15-3. Interrupt Mask Register High (IMRHn)
Table 15-6. IMRHn Field Descriptions
Field
Description
31–0
INT_MASK
Interrupt mask. Each bit corresponds to an interrupt source. The corresponding IMRHn bit determines whether an
interrupt condition can generate an interrupt. The corresponding IPRHn bit reflects the state of the interrupt signal
even if the corresponding IMRHn bit is set.
0 The corresponding interrupt source is not masked
1 The corresponding interrupt source is masked
IPSBAR
Offset:
0x00_0C0C (IMRL0)
0x00_0D0C (IMRL1)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
INT_MASK[31:1]
MASK
ALL
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
Figure 15-4. Interrupt Mask Register Low (IMRLn)
Table 15-7. IMRLn Field Descriptions
Field
Description
31–1
INT_MASK
Interrupt mask. Each bit corresponds to an interrupt source. The corresponding IMRLn bit determines whether an
interrupt condition can generate an interrupt. The corresponding IPRLn bit reflects the state of the interrupt signal
even if the corresponding IMRLn bit is set.
0 The corresponding interrupt source is not masked
1 The corresponding interrupt source is masked
0
MASKALL
Mask all interrupts. Setting this bit forces the other 63 bits of the IMRHn and IMRLn to ones, disabling all interrupt
sources, and providing a global mask-all capability.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
