ColdFire Flash Module (CFM)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
17-15
17.3.3.9
CFMCLKSEL — CFM Clock Select Register
The CFMCLKSEL register reflects the factory setting for read access latency from the system bus to the
flash block.
Figure 17-13. CFM Clock Select Register (CFMCLKSEL)
CFMCLKSEL register bits [1:0] are read-only, while the remaining bits read 0 and are not writable.
Table 17-13. CFM Flash Memory Commands
CMD[6:0]
Description
0x05
Blank Check
0x06
Page Erase Verify
0x20
Word Program
0x40
Page Erase
0x41
Mass Erase
IPSBAR
Offset: 0x1D_004A(
CFMCLKSEL
)
Access: User read/write
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CLKSEL
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
1
1
Reset state set by factory.
F
1
Table 17-14. CFMCLKSEL Field Descriptions
Field
Description
15 - 2
Reserved, should read 0
1 - 0
CLKSEL
Flash read access latency select
The CLKSEL bits set the read access latency to the flash block.
describes the setting that
selects between single-cycle and two-cycle flash block read access.
Table 17-15. Clock Select States
CLKSEL[1:0]
Description
Burst Read Access
2’b10
Single-Cycle Flash Block Read Access
1-1-1-1
All other combinations
Two-cycle Flash Block Read Access
2-1-1-1
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
