Fast Ethernet Controller (FEC)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
18-17
18.4.14 Ethernet Error-Handling Procedure
The Ethernet controller reports frame reception and transmission error conditions using the FEC RxBDs,
the EIR register, and the MIB block counters.
18.4.14.1 Transmission Errors
18.4.14.1.1
Transmitter Underrun
If this error occurs, the FEC sends 32 bits that ensure a CRC error and stops transmitting. All remaining
buffers for that frame are then flushed and closed. The UN bit is set in the EIR. The FEC then continues
to the next transmit buffer descriptor and begin transmitting the next frame.
The UN interrupt is asserted if enabled in the EIMR register.
18.4.14.1.2
Retransmission Attempts Limit Expired
When this error occurs, the FEC terminates transmission. All remaining buffers for that frame are flushed
and closed, and the RL bit is set in the EIR. The FEC then continues to the next transmit buffer descriptor
and begin transmitting the next frame.
The RL interrupt is asserted if enabled in the EIMR register.
18.4.14.1.3
Late Collision
When a collision occurs after the slot time (512 bits starting at the Preamble), the FEC terminates
transmission. All remaining buffers for that frame are flushed and closed, and the LC bit is set in the EIR
register. The FEC then continues to the next transmit buffer descriptor and begin transmitting the next
frame.
The LC interrupt is asserted if enabled in the EIMR register.
18.4.14.1.4
Heartbeat
Some transceivers have a self-test feature called heartbeat or signal quality error. To signify a good
self-test, the transceiver indicates a collision to the FEC within 4 microseconds after completion of a frame
transmitted by the Ethernet controller. This indication of a collision does not imply a real collision error
on the network, but is rather an indication that the transceiver seems to be functioning properly. This is
called the heartbeat condition.
If the HBC bit is set in the TCR register and the heartbeat condition is not detected by the FEC after a frame
transmission, then a heartbeat error occurs. When this error occurs, the FEC closes the buffer, sets the HB
bit in the EIR register, and generates the HBERR interrupt if it is enabled.
18.4.14.2 Reception Errors
18.4.14.2.1
Overrun Error
If the receive block has data to put into the receive FIFO and the receive FIFO is full, the FEC sets the OV
bit in the RxBD. All subsequent data in the frame is discarded and subsequent frames may also be
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MCF52235CVM60
