Fast Ethernet Controller (FEC)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
18-46
Freescale Semiconductor
18.5.4.23 Receive Buffer Size Register (EMRBR)
The EMRBR is a 9-bit register programmed by the user. The EMRBR register dictates the maximum size
of all receive buffers. Because receive frames are truncated at 2k-1 bytes, only bits 10–4 are used. This
value should take into consideration that the receive CRC is always written into the last receive buffer. To
allow one maximum size frame per buffer, EMRBR must be set to RCR[MAX_FL] or larger. The EMRBR
must be evenly divisible by 16. To ensure this, bits 3-0 are forced low. To minimize bus utilization
(descriptor fetches) it is recommended that EMRBR be greater than or equal to 256 bytes.
The EMRBR register does not reset, and must be initialized by the user.
IPSBAR
Offset: 0x1188 (EMRBR)
Access: User read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Undefined
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
R_BUF_SIZE
0
0
0
0
W
Reset
Undefined
Figure 18-26. Receive Buffer Size Register (EMRBR)
Table 18-35. EMRBR Field Descriptions
Field
Description
30–11
Reserved, should be cleared.
10–4
R_BUF_SIZE
Receive buffer size.
3–0
Reserved, should be cleared.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
