Ethernet Physical Transceiver (EPHY)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
19-23
19.4.1
Power Down/Initialization
Upon reset, the EPHYEN bit, in the Ethernet physical transceiver control register 0 (EPHYCTL0), is
cleared and EPHY is in its lowest power consumption state. All analog circuits are powered down. The
twisted-pair transmitter and receiver pins (PHY_TXP, PHY_TXN, PHY_RXP, and PHY_RXN) are
high-impedance. The MII management interface is not accessible. All MII registers are initialized to their
reset state. The ANDIS, DIS100, and DIS10 bits, in the EPHYCTL0 register, have no effect until the
EPHYEN bit is set.
The EPHYEN bit can be set or cleared by a register write at any time. Prior to enabling the EPHY, setting
EPHYEN to 1, the MII PHY address PHYADD[4:0] must be set in the Ethernet physical transceiver
control register 1 (EPHYCTL1), and the ANDIS, DIS100, DIS10 bits, in the EPHYCTL0 register, must
be configured for the desired start-up operation. When the EPHYEN bit transitions from 0 to 1, MDIO
communications must be delayed until completion of a start-up delay period (t
Start-up
, see
).
Figure 19-18. EPHY Start-Up / Initialization Sequence
RESET or EPHYEN=0
Set PHYADD[4:0],
ANDIS, DIS100, and DIS10
Configure MII registers
via MDIO
Initialization Complete
Set EPHYEN=1
PHYADD[4:0] and ANDIS
become latched in MII registers
Delay for tStart-up
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
