DMA Controller Module
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
20-13
20.4.3
Channel Initialization and Startup
Before a block transfer starts, channel registers must be initialized with information describing
configuration, request-generation method, and the data block.
20.4.3.1
Channel Prioritization
The four DMA channels are prioritized in ascending order (channel 0 having highest priority and channel
3 having the lowest) or in an order determined by DCR
n
[BWC]. If the BWC encoding for a DMA channel
is 000, that channel has priority only over the channel immediately preceding it. For example, if
DCR3[BWC] equals 000, DMA channel 3 has priority over DMA channel 2 (assuming
DCR2[BWC]
≠
000), but not over DMA channel 1.
If DCR0[BWC] equals 000 and DCR1[BWC] equals 000, DMA0 continues having priority over DMA1.
In this case, DCR1[BWC] equals 000 does not affect prioritization.
Simultaneous external requests are prioritized in ascending order or in an order determined by each
channel’s DCR
n
[BWC] bits.
20.4.3.2
Programming the DMA Controller Module
General guidelines for programming the DMA are:
•
No mechanism exists within the DMA module itself to prevent writes to control registers during
DMA accesses.
•
If the DCR
n
[BWC] value of sequential channels are equal, the channels are prioritized in
ascending order.
The DMAREQC register is configured to assign peripheral DMA requests to the individual DMA
channels.
The SAR
n
is loaded with the source (read) address. If the transfer is from a peripheral device to memory,
the source address is the location of the peripheral data register. If the transfer is from memory to a
peripheral device or memory, the source address is the starting address of the data block. This can be any
aligned byte address.
The DAR
n
should contain the destination (write) address. If the transfer is from a peripheral device to
memory, or from memory to memory, the DAR
n
is loaded with the starting address of the data block to be
written. If the transfer is from memory to a peripheral device, DAR
n
is loaded with the address of the
peripheral data register. This address can be any aligned byte address.
SAR
n
and DAR
n
change after each cycle depending on DCR
n
[SSIZE,DSIZE,
SINC,DINC,SMOD,DMOD] and on the starting address. Increment values can be 1, 2, 4, or 16 for byte,
word, longword, or 16-byte line transfers, respectively. If the address register is programmed to remain
unchanged (no count), the register is not incremented after the data transfer.
BCR
n
[BCR] must be loaded with the number of byte transfers to occur. It is decremented by 1, 2, 4, or 16
at the end of each transfer, depending on the transfer size. DSR
n
[DONE] must be cleared for channel
startup.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
