UART Modules
26-18
Freescale Semiconductor
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Using a 60-MHz internal bus clock and letting baud rate equal 9600, then
Eqn. 26-2
Therefore, UBG1
n
equals 0x00 and UBG2
n
equals 0xC3.
26.4.1.2.2
External Clock
An external source clock (DTIN
n
) passes through a divide-by-1 or 16 prescaler. If f
extc
is the external clock
frequency, baud rate can be described with this equation:
Eqn. 26-3
26.4.2
Transmitter and Receiver Operating Modes
is a functional block diagram of the transmitter and receiver showing the command and
operating registers, which are described generally in the following sections. For detailed descriptions, refer
to
Section 26.3, “Memory Map/Register Definition
.”
Figure 26-18. Transmitter and Receiver Functional Diagram
26.4.2.1
Transmitter
The transmitter is enabled through the UART command register (UCR
n
). When it is ready to accept a
character, UART sets USR
n
[TXRDY]. The transmitter converts parallel data from the CPU to a serial bit
stream on UTXD
n
. It automatically sends a start bit followed by the programmed number of data bits, an
Divider
60
10
6
×
Hz
32
9600
×
Hz
[
]
--------------------------------------
195
decimal
(
)
0x00C3
hexadecimal
(
)
=
=
=
Baudrate
f
extc
(16 or 1)
---------------------
=
Receiver Shift Register
UART Command Register (UCRn)
W
UART Status Register (USRn)
R
Transmitter Shift Register
UART Mode Register 1 (UMR1n)
R/W
UART Mode Register 2 (UMR2n)
R/W
Transmitter Holding Register
W
Receiver Holding Register 3
Receiver Holding Register 2
Receiver Holding Register 1
R
UART Receive
UART
Buffer (URBn)
(4 Registers)
UARTn
External
Interface
Transmit Buffer
(UTBn)
(2 Registers)
FIFO
URXDn
UTXDn
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
