UART Modules
26-22
Freescale Semiconductor
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
programming the ERR bit in the UART’s mode register (UMR1
n
), status is provided in character or block
modes.
USR
n
[RXRDY] is set when at least one character is available to be read by the CPU. A read of the receive
buffer produces an output of data from the top of the FIFO. After the read cycle, the data at the top of the
FIFO and its associated status bits are popped and the receiver shift register can add new data at the bottom
of the FIFO. The FIFO-full status bit (FFULL) is set if all three positions are filled with data. The RXRDY
or FFULL bit can be selected to cause an interrupt and TXRDY or RXRDY can be used to generate a DMA
request.
The two error modes are selected by UMR1
n
[ERR]:
•
In character mode (UMR1
n
[ERR] = 0), status is given in the USR
n
for the character at the top of
the FIFO.
•
In block mode, the USR
n
shows a logical OR of all characters reaching the top of the FIFO since
the last RESET ERROR STATUS command. Status is updated as characters reach the top of the
FIFO. Block mode offers a data-reception speed advantage where the software overhead of
error-checking each character cannot be tolerated. However, errors are not detected until the check
is performed at the end of an entire message—the faulting character is not identified.
In either mode, reading the USR
n
does not affect the FIFO. The FIFO is popped only when the receive
buffer is read. The USR
n
should be read before reading the receive buffer. If all three receiver holding
registers are full, a new character is held in the receiver shift register until space is available. However, if
a second new character is received, the contents of the character in the receiver shift register is lost, the
FIFOs are unaffected, and USR
n
[OE] is set when the receiver detects the start bit of the new overrunning
character.
To support flow control, the receiver can be programmed to automatically negate and assert URTS
n
, in
which case the receiver automatically negates URTS
n
when a valid start bit is detected and the FIFO is
full. The receiver asserts URTS
n
when a FIFO position becomes available; therefore, connecting URTS
n
to the UCTS
n
input of the transmitting device can prevent overrun errors.
NOTE
The receiver continues reading characters in the FIFO if the receiver is
disabled. If the receiver is reset, the FIFO, URTS
n
control, all receiver status
bits, interrupts, and DMA requests are reset. No more characters are
received until the receiver is reenabled.
26.4.3
Looping Modes
The UART can be configured to operate in various looping modes. These modes are useful for local and
remote system diagnostic functions. The modes are described in the following paragraphs and in
Section 26.3, “Memory Map/Register Definition.”
The UART’s transmitter and receiver should be disabled when switching between modes. The selected
mode is activated immediately upon mode selection, regardless of whether a character is being received
or transmitted.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
