Analog-to-Digital Converter (ADC)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
28-4
12
SYNC0
Synchronization 0 Enable bit. When this bit is set, a conversion may be initiated by asserting a positive edge
on the SYNC0 input. Any subsequent SYNC0 input pulses that occur during the scan are ignored. In once
sequential and once parallel scan modes, only the first SYNC0 input pulse is honored. Subsequent SYNC0
input pulses are ignored until SYNC0 input is re-armed by setting SYNC0. This can be done at any time, even
during the execution of the scan. The ADC must be in a stable power configuration prior to writing to START0
(see
Section 28.5.8, “Power Management
”).
0 Scan is initiated by a write to the START0 bit only
1 Scan is initiated by a SYNC0 input pulse or a write to the START0 bit
11
EOSIE0
End of Scan Interrupt 0 Enable bit. This bit enables an EOSI0 interrupt to be generated upon completion of
the scan. For looping scan modes, the interrupt triggers after the completion of each iteration of the loop.
0 Interrupt disabled
1 Interrupt enabled
10
ZCIE
Zero Crossing Interrupt Enable bit. This bit enables the zero crossing interrupt if the current result value has
a sign change from the previous result as configured by the ADZCC register.
0 Interrupt disabled
1 Interrupt enabled
9
LLMTIE
Low Limit Interrupt Enable bit. This bit enables the low limit exceeded interrupt when the current result value
is less than the low limit register value. The raw result value is compared to ADLLMTn[LLMT] before the offset
register value is subtracted.
0 Interrupt disabled
1 Interrupt enabled
8
HLMTIE
High Limit Interrupt Enable bit. This bit enables the high limit exceeded interrupt if the current result value is
greater than the high limit register value. The raw result value is compared to ADHLMT[HLMT] before the
offset register value is subtracted.
0 Interrupt disabled
1 Interrupt enabled
Table 28-2. CTRL1 Field Descriptions (continued)
Field
Description
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International
Trade
Commission,
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to
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MCF52235CVM60