Analog-to-Digital Converter (ADC)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
28-8
28.4.3
Zero Crossing Control Register (ADZCC)
The ADC zero crossing control (ADZCC) register provides the ability to monitor the selected channels
and determine the direction of zero crossing triggering the optional interrupt. Zero crossing logic monitors
only the sign change between current and previous sample. The ZCE0 bit monitors the sample stored in
ADRSLT0, ZCE1 bit monitors ADRSLT1, and ZCE7 bit monitors ADRSLT7. When the zero crossing is
disabled for a selected result register, sign changes are not monitored or updated in the ADZCSTAT
register.
28.4.4
Channel List 1 and 2 Registers (ADLST1 and ADLST2)
The channel list register contains an ordered list of the analog input channels to be converted when the next
scan is initiated. If all samples are enabled in the ADSDIS register, a sequential scan of inputs proceeds in
order of SAMPLE0 through SAMPLE7. If one of the parallel sampling modes is selected instead, the
converter A sampling order is SAMPLE0-3, and the converter B sampling order is SAMPLE4-7.
In sequential modes, the sample slots are converted in order from SAMPLE0 to SAMPLE7. Analog input
pins can be sampled in any order, including sampling the same input pin more than once.
In parallel modes, converter A processes sample slots SAMPLE0 through SAMPLE3, while converter B
processes sample slots SAMPLE4 through SAMPLE7. Because converter A only has access to analog
inputs AN0 through AN3, sample slots SAMPLE0-3 should only contain binary values between 000 and
011. Likewise, because converter B only has access to analog inputs AN4 through AN7, sample slots
—
—
—
—
—
—
11111
64
100 kHz
62.5 kHz
500 kHz
CLK/128
IPSBAR
Offset: 0x19_0004 (ADZCC)
Access: read/write
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
ZCE7
ZCE6
ZCE5
ZCE4
ZCE3
ZCE2
ZCE1
ZCE0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 28-5. Zero Crossing Control Register (ADZCC)
Table 28-6. ADZCC Field Descriptions
Field
Description
15–0
ZCEn
Zero Crossing Enable. For each channel n, setting the ZCEn field allows detection of the indicated zero
crossing condition, provided the corresponding offset register (ADOFSn) has a value offset, 0 < offset <
0x7FF8.
00 Zero crossing disabled
01 Zero crossing enabled for positive to negative sign change
10 Zero crossing enabled for negative to positive sign change
11 Zero crossing enabled for any sign change
Table 28-5. ADC Clock Frequency for Various Conversion Clock Sources (continued)
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
