Analog-to-Digital Converter (ADC)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
28-28
Figure 28-23. Result Register Data Manipulation
28.5.4
Sequential vs. Parallel Sampling
All scan modes make use of the 8 SAMPLE slots in the ADLST1 and ADLST2 registers. These slots are
used to define which single-ended input or differential input pair is measured at each step in a scan
sequence. The SDIS register is used to disable unneeded slots.
Differential measurements are made on input pairs AN0/1, AN2/3, AN4/5, and AN6/7 using the CHNCFG
field of the CTRL1 register. A single ended measurement is made if a SAMPLE slot refers to an input not
configured as a member of a differential pair by CHNCFG. A differential measurement is made if a
SAMPLE slot refers to either member of a differential pair. Refer to the CHNCFG field description in the
CTRL1 register for details of differential and single ended measurement.
Scan modes are sequential or parallel, as defined by the SMODE field of the CTRL1 register. In
sequential scans, up to 8 SAMPLE slots are sampled one at a time in the order SAMPLE 0-7. Each
SAMPLE slot may refer to any of the 8 analog inputs (AN0-7), thus the same input may be referenced by
more than one SAMPLE slot. Scanning is initiated when the START0 bit is written as 1 or, if the SYNC0
V+
V–
ADCA
12
12
+
ADOFS[0:3]
13
Zero Crossing Logic
+
–
ADHLMT[4:7]
>
ADRSLT[0:3]
Zero Crossing
or Error Limit
Interrupt
ADLLMT[4:7]
<
12
12
+
ADOFS[4:7]
13
Zero Crossing Logic
+
–
ADRSLT[4:7]
12
V+
V–
ADCB
12
ADHLMT[0:3]
>
ADLLMT[0:3]
<
Test Data
(From CPU)
Test Data
(From CPU)
ADC2
ADC1
ADC0
End of
Scan B
Interrupt
End of
Scan A
Interrupt
IRQ Logic
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
