Pulse-Width Modulation (PWM) Module
29-15
Freescale Semiconductor
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
29.3.1.2
Scaled Clock (SA or SB)
The scaled A (SA) and scaled B (SB) clocks use clock A and B respectively as inputs, divide it further with
a user programmable value, then divide this by 2. The rates available for clock SA are programmable to
run at clock A divided by 2, 4,..., or 512. Similar rates are available for clock SB.
Clock SA equals clock A divided by two times the value in the PWMSCLA register:
Eqn. 29-5
Similarly, clock SB is generated according to the following equation:
Eqn. 29-6
As an example, consider the case in which the user writes 0xFF into the PWMSCLA register. Clock A for
this case is selected to be internal bus clock divided by 4. A pulse occurs at a rate of once every 255
×
4 bus
cycles. Passing this through the divide by two circuit produces a clock signal of the internal bus clock
divided by 2040. Similarly, a value of 0x01 in the PWMSCLA register when clock A is internal bus clock
divided by 4 produces an internal bus clock divided by 8 rate.
Writing to PWMSCLA or PWMSCLB causes the associated 8-bit down counter to be re-loaded.
Otherwise, when changing rates, the counter would have to count down to 0x01 before counting at the
proper rate. Forcing the associated counter to re-load the scale register value every time PWMSCLA or
PWMSCLB is written prevents this.
Writing to the scale registers while channels are operating can cause irregularities in the PWM outputs.
29.3.1.3
Clock Select
Each PWM channel has the capability of selecting one of two clocks. For channels 0, 1, 4, and 5 the clock
choices are clock A or SA. For channels 2, 3, 6 and 7, the choices are clock B or SB. The clock selection
is done with the PWMCLK[PCLK
x
] control bits.
Changing clock control bits while channels are operating can cause irregularities in the PWM outputs.
29.3.2
PWM Channel Timers
The main part of the PWM module is the actual timers. Each of the timer channels has a counter, a period
register, and a duty register (each are 8-bit). The waveform output period is controlled by a match between
the period register and the value in the counter. The duty is controlled by a match between the duty register
and the counter value and causes the state of the output to change during the period. The starting polarity
of the output is also selectable on a per channel basis.
shows a block diagram for a PWM
timer.
Clock SA
Clock A
2
PWMSCLA
×
-----------------------------------------
=
Clock SB
Clock B
2
PWMSCLB
×
----------------------------------------
=
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
