ColdFire Core
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
3-13
Figure 3-14. V2 OEP Register-to-Memory
The pipeline timing diagrams of
depict the execution templates for these three classes of
instructions. In these diagrams, the x-axis represents time, and the various instruction operations are shown
progressing down the operand execution pipeline.
Operand Execution Pipeline
DSOC
AGEX
Opword
Extension 1
Extension 2
Core Bus
Read Data
Core Bus
Address
Core Bus
Write
RGF
Data
Ax
d16
Ry
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MCF52235CVM60
