FlexCAN
30-7
Freescale Semiconductor
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
28
HALT
Halt FlexCAN. Setting this bit puts the FlexCAN module into freeze mode. It has the same effect as assertion of the
BKPT signal. This bit is set after reset and should be cleared after initializing the message buffers and control
registers. FlexCAN message buffer receive and transmit functions are inactive until this bit is cleared. While in
freeze mode, the CPU has write access to the error counter register (ERRCNT) that is otherwise read-only.
0 The FlexCAN operates normally
1 FlexCAN enters freeze mode if FRZ equals 1
27
NOTRDY
FlexCAN not ready. This bit indicates that the FlexCAN is in disable or freeze mode. This bit is read-only and it is
cleared after the FlexCAN exits these modes.
0 FlexCAN is in normal mode, listen-only mode, or loop-back mode.
h1FlexCAN is in disable or freeze mode.
26
Reserved, must be cleared.
25
SOFTRST
Soft reset. When set, the FlexCAN resets its internal state machines (sequencer, error counters, error flags, and
timer) and the host interface registers (CANMCR [except the MDIS bit], TIMER, ERRCNT, ERRSTAT, IMASK, and
IFLAG).
The configuration registers that control the interface with the CAN bus are not changed (CANCTRL, RXGMASK,
RX14MASK, RX15MASK). Message buffers are also not changed. This allows SOFTRST to be used as a debug
feature while the system is running.
Because soft reset is synchronous and has to follow a request/acknowledge procedure across clock domains, it
may take some time to fully propagate its effect. The SOFTRST bit remains set while reset is pending and is
automatically cleared when reset completes. The user should poll this bit to know when the soft reset has
completed.
0 Soft reset cycle completed
1 Soft reset cycle initiated
24
FRZACK
Freeze acknowledge. Indicates that the FlexCAN module has entered freeze mode. The user should poll this bit
after freeze mode has been requested, to know when the module has actually entered freeze mode. When freeze
mode is exited, this bit is cleared after the FlexCAN prescaler is enabled. This is a read-only bit.
0 The FlexCAN has exited freeze mode and the prescaler is enabled.
1 The FlexCAN has entered freeze mode, and the prescaler is disabled.
23
SUPV
Supervisor/user data space. Places the FlexCAN registers in supervisor or user data space.
0 Registers with access controlled by the SUPV bit are accessible in user or supervisor privilege mode.
1 Registers with access controlled by the SUPV bit are restricted to supervisor mode.
22–21
Reserved, must be cleared.
20
LPMACK
Low power mode acknowledge. Indicates that FlexCAN is disabled. Disabled mode cannot be entered until all
current transmission or reception processes have finished, so the CPU can poll the LPMACK bit to know when the
FlexCAN has actually entered low power mode. See
Section 30.1.3.3, “Module Disabled Mode,”
for more information. This bit is read-only.
0 FlexCAN not disabled.
1 FlexCAN is in disabled mode.
19–4
Reserved, must be cleared.
3–0
MAXMB
Maximum number of message buffers. Defines the maximum number of message buffers that take part in the
matching and arbitration process. The reset value (0xF) is equivalent to16 message buffer (MB) configuration. This
field should be changed only while the module is in freeze mode.
Note:
Table 30-2. CANMCR Field Descriptions (continued)
Field
Description
Maximum MBs in Use = MAXMB + 1
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
