FlexCAN
Freescale Semiconductor
30-12
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
30.3.5
FlexCAN Error Counter Register (ERRCNT)
This register has two 8-bit fields reflecting the value of two FlexCAN error counters: transmit error counter
(TXECTR) and receive error counter (RXECTR). The rules for increasing and decreasing these counters
are described in the CAN protocol and are completely implemented in the FlexCAN module. Both
counters are read-only, except in freeze mode, where they can be written by the CPU.
Writing to the ERRCNT register while in freeze mode is an indirect operation. The data is first written to
an auxiliary register, then an internal request/acknowledge procedure across clock domains is executed.
All this is transparent to the user, except for the fact that the data takes some time to be actually written to
the register. If desired, software can poll the register to discover when the data was actually written.
FlexCAN responds to any bus state as described in the protocol, e.g. transmit error-active or error-passive
flag, delay its transmission start time (error-passive), and avoid any influence on the bus when in bus off
state. The following are the basic rules for FlexCAN bus state transitions:
•
If the value of TXECTR or RXECTR increases to be greater than or equal to 128, the FLTCONF
field in the error and status register (ERRSTAT) is updated to reflect error-passive state.
•
If the FlexCAN state is error-passive, and TXECTR or RXECTR decrements to a value less than
or equal to 127 while the other already satisfies this condition, the ERRSTAT[FLTCONF] field is
updated to reflect error-active state.
•
If the value of TXECTR increases to be greater than 255, the ERRSTAT[FLTCONF] field is
updated to reflect bus off state, and an interrupt may be issued. The value of TXECTR is then reset
to zero.
4
Mismatch for MB2 because of ID28.
5
Mismatch for MB3 because of ID28, Match for MB14 (Uses RX14MASK).
6
Mismatch for MB14 because of ID27 (Uses RX14MASK).
7
Match for MB14 (Uses RX14MASK).
IPSBAR
Offsets:
0x1C_0010 (RXGMASK)
0x1C_0014 (RX14MASK)
0x1C_0018 (RX15MASK)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R 0 0 0
MI
Standard ID
MI
Extended ID
W
Reset 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Figure 30-7. FlexCAN Rx Mask Registers (RXGMASK, RX14MASK, RX15MASK)
Table 30-6. RXxxMASK Field Descriptions
Field
Description
31–29
Reserved, must be cleared.
28–18
MI28–18
Standard ID mask bits. These bits are the same mask bits for the Standard and Extended Formats.
17–0
MI17–0
Extended ID mask bits. These bits are used to mask comparison only in Extended Format.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
