ColdFire Core
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
3-15
summarizes the instructions added to revision ISA_A to form revision ISA_A+. For more details
see the
ColdFire Family Programmer’s Reference Manual
.
3.3.3
Exception Processing Overview
Exception processing for ColdFire processors is streamlined for performance. The ColdFire processors
differ from the M68000 family because they include:
•
A simplified exception vector table
•
Reduced relocation capabilities using the vector-base register
•
A single exception stack frame format
•
Use of separate system stack pointers for user and supervisor modes.
All ColdFire processors use an instruction restart exception model. However, Version 2 ColdFire
processors require more software support to recover from certain access errors. See
Exception processing includes all actions from fault condition detection to the initiation of fetch for first
handler instruction. Exception processing is comprised of four major steps:
1. The processor makes an internal copy of the SR and then enters supervisor mode by setting the S
bit and disabling trace mode by clearing the T bit. The interrupt exception also forces the M bit to
be cleared and the interrupt priority mask to set to current interrupt request level.
Table 3-4. Instruction Enhancements over Revision ISA_A
Instruction
Description
BITREV
The contents of the destination data register are bit-reversed; new Dn[31] equals old Dn[0], new
Dn[30] equals old Dn[1],..., new Dn[0] equals old Dn[31].
BYTEREV
The contents of the destination data register are byte-reversed; new Dn[31:24] equals old
Dn[7:0],..., new Dn[7:0] equals old Dn[31:24].
FF1
The data register, Dn, is scanned, beginning from the most-significant bit (Dn[31]) and ending
with the least-significant bit (Dn[0]), searching for the first set bit. The data register is then
loaded with the offset count from bit 31 where the first set bit appears.
Move from USP USP
→
Destination register
Move to USP
Source register
→
USP
STLDSR
Pushes the contents of the status register onto the stack and then reloads the status register
with the immediate data value.
2. The processor determines the exception vector number. For all faults except interrupts, the
processor performs this calculation based on exception type. For interrupts, the processor
performs an interrupt-acknowledge (IACK) bus cycle to obtain the vector number from the
interrupt controller. The IACK cycle is mapped to special locations within the interrupt
controller’s address space with the interrupt level encoded in the address.
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Commission,
BGA-packaged
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prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
