FlexCAN
30-23
Freescale Semiconductor
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
does not receive frames transmitted by itself if another device on the CAN bus has an ID that matches the
FlexCAN Rx MB ID.
30.3.14 Matching Process
The matching process is an algorithm that scans the entire MB memory looking for Rx MBs programmed
with the same ID as the one received from the CAN bus. Only MBs programmed to receive participate in
the matching process for received frames.
While the ID, DLC and data fields are retrieved from the CAN bus, they are stored temporarily in the serial
message buffer. The matching process takes place during the CRC field. If a matching ID is found in one
of the MBs, the contents of the SMB are transferred to the matched MB during the sixth bit of the
end-of-frame field of the CAN protocol. This operation is called move-in. If any protocol error (CRC,
ACK, etc.) is detected, than the move-in operation does not happen.
An MB with a matching ID is free to receive a new frame if the MB is not locked (see
“Locking and Releasing Message Buffers”
). The CODE field is EMPTY, FULL, or OVERRUN but the
CPU has already serviced the MB (read the C/S word and then unlocked the MB).
Matching to a range of IDs is possible by using ID acceptance masks. FlexCAN supports a masking
scheme with three mask registers (RXGMASK, RX14MASK, and RX15MASK). During the matching
algorithm, if a mask bit is asserted, then the corresponding ID bit is compared. If the mask bit is negated,
the corresponding ID bit is don’t care.
30.3.15 Message Buffer Managing
To maintain data coherency and FlexCAN proper operation, the CPU must obey the rules described in
Section 30.3.11, “Transmit Process”
and
Section 30.3.13, “Receive Process.”
Any form of CPU accessing
a MB structure within FlexCAN other than those specified may cause FlexCAN to behave in an
unpredictable way.
30.3.15.1 Message Buffer Deactivation
If the CPU wants to change the function of an active MB, the recommended procedure is to put the module
into freeze mode and then change the CODE field of that MB. This is a safe procedure because the
FlexCAN waits for pending CAN bus and MB moving activities to finish before entering freeze mode.
Nevertheless, a mechanism is provided to maintain data coherence when the CPU writes to the control and
status word of active MBs out of freeze mode.
Any CPU write access to the C/S word of an MB causes that MB to be excluded from the transmit or
receive processes during the current matching or arbitration round. This mechanism is called MB
deactivation. It is temporary, affecting only for the current match/arbitration round.
The purpose of deactivation is data coherency. The match/arbitration process scans the MBs to decide
which MB to transmit or receive. If the CPU updates the MB in the middle of a match or arbitration
process, the data of that MB may no longer be coherent; therefore, that MB is deactivated.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
