Debug Module
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
31-9
31.3.4
Address Attribute Trigger Register (AATR)
The AATR defines address attributes and a mask to be matched in the trigger. The register value is
compared with address attribute signals from the processor’s local high-speed bus, as defined by the
setting of the trigger definition register (TDR). AATR is accessible in supervisor mode as debug control
register 0x06 using the WDEBUG instruction and through the BDM port using the
WDMREG
command.
DRc[4:0]: 0x06 (AATR)
Access: Supervisor write-only
BDM write-only
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
RM
SZM
TTM
TMM
R
SZ
TT
TM
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
Figure 31-4. Address Attribute Trigger Register (AATR)
Table 31-7. AATR Field Descriptions
Field
Description
15
RM
Read/write Mask. Setting RM masks R in address comparisons.
14–13
SZM
Size Mask. Setting an SZM bit masks the corresponding SZ bit in address comparisons.
12–11
TTM
Transfer Type Mask. Setting a TTM bit masks the corresponding TT bit in address comparisons.
10–8
TMM
Transfer Modifier Mask. Setting a TMM bit masks the corresponding TM bit in address comparisons.
7
R
Read/Write. R is compared with the R/W signal of the processor’s local bus.
6–5
SZ
Size. Compared to the processor’s local bus size signals.
00 Longword
01 Byte
10 Word
11 Reserved
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
