Revision History
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
B-9
Freescale Semiconductor
B.6
Changes between Rev. 0 and Rev. 1
Section 28.5.7 / Page 28-32 Deleted extraneous sentence at end of first paragraph.
Figure 28-15 / Page 28-26
Changed address of CTRL2 register from 0x19_0001 to 0x19_0002.
Table 31-5 / Page 31-8
Added bit description for the BKD bit in the Configuration/Status Register (CSR).
Section 32.4.3 / Page 32-7
Added missing Table 32-5 (JTAG instructions).
Table A-3
• Corrected spelling of IPSBAR for the ICR034, ICR134, and GPTACFORC registers.
• Added missing registers CFMCLKSEL, ICR016, and ICR116.
• Added leading zeros to addresses as necessary to adhere to four-digit address convention.
• Corrected address of the PPMRH, PPMRL, and GPTAPACNT registers.
• Corrected addresses of the DMA controller module registers to match the values in the text.
• Corrected several GPIO register names to match the memory map.
• Corrected several real-time clock register names.
• Updated ADC register entries to show correct register names, addresses, and bit sizes.
Table 6. MCF52235RM Rev. 0 to Rev. 1 Changes
Location in Rev. 0
Description
Throughout
Corrected various spelling, grammar, style, cross-reference, and layout errors.
Table 2-1 / Section 2.2
• Added pin assignments to 121MAPBGA packaging.
• Added footnote describing limited functionality when using external PHY.
• Corrected various pin assignments and functions.
• Deleted duplicate CANTX and CANRX footnote.
Chapter 7
Removed references to 1:1 PLL mode, as it is not available on MCF521x and MCF522xx parts.
Figure 7-1 / Page 7-3
Added PLL pre-divider block.
Table 7-3 / Page 7-5
Added register name (CCHR) to Clock Control High Register and changed reset value from 0x00
to 0x04.
Table 7-4 / Page 7-7
In the description for MFD, changed footnote 1 to include correct equations and values.
Section 7.7.1.4 / Page 7-10
Changed register name from PFD to CCHR and changed reset value from 0b000 to 0b100.
Section 7.8.2 / Page 7-11
Added text to first sentence to: “... reference frequency (i.e., clock frequency divided by the
pre-division factor specified by CCHR)...”
Table 8-1 / Section 8.2
Corrected first column to display the proper IPSBAR offset.
Chapter 8
Corrected the addresses in the register figures to show the proper IPSBAR address instead of
$BASE_ADDRESS address.
Fig. 8-13 / Page 8-14
Deleted invalid reference to ARM instruction code segment.
Table 9-3/ Page 9-3
• Corrected field order - Bit 13 is CDRNGA, Bit 12 is CDEPHY.
• In description for CDGPT, replaced “ICOC” with “GPT”.
Section 9.2.4.1 / Page 9-9
Corrected LPCR figure and table - STPMD is a 2-bit field (bits 4 and 3), and bit 1 is LVDSE.
Chapter 11
Corrected conditional text entries to ensure proper display of memory sizes.
Table 11-2 / Page 11-3
Filled in table in PRIU/PRIL field description.
Figure 14-1 / Page 14-2
Added FEC signals and arranged signals in same order as in Table 2-1.
Table 5. MCF52235RM Rev. 1 to Rev. 2 Changes (continued)
Location in Rev. 1
Description
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
