Enhanced Multiply-Accumulate Unit (EMAC)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
4-5
summarizes the interaction of the MACSR[S/U,F/I,R/T] control bits.
4.2.2
Mask Register (MASK)
The 32-bit MASK implements the low-order 16 bits to minimize the alignment complications involved
with loading and storing only 16 bits. When the MASK is loaded, the low-order 16 bits of the source
operand are actually loaded into the register. When it is stored, the upper 16 bits are all forced to ones.
This register performs a simple AND with the operand address for MAC instructions. The processor
calculates the normal operand address and, if enabled, that address is then ANDed with {0xFFFF,
MASK[15:0]} to form the final address. Therefore, with certain MASK bits cleared, the operand address
3
N
Negative. Set if the msb of the result is set, otherwise cleared. N is affected only by MAC, MSAC, and load
operations; it is not affected by MULS and MULU instructions.
2
Z
Zero. Set if the result equals zero, otherwise cleared. This bit is affected only by MAC, MSAC, and load
operations; it is not affected by MULS and MULU instructions.
1
V
Overflow. Set if an arithmetic overflow occurs on a MAC or MSAC instruction, indicating that the result
cannot be represented in the limited width of the EMAC. V is set only if a product overflow occurs or the
accumulation overflows the 48-bit structure. V is evaluated on each MAC or MSAC operation and uses the
appropriate PAVn flag in the next-state V evaluation.
0
EV
Extension overflow. Signals that the last MAC or MSAC instruction overflowed the 32 lsbs in integer mode
or the 40 lsbs in fractional mode of the destination accumulator. However, the result remains accurately
represented in the combined 48-bit accumulator structure. Although an overflow has occurred, the correct
result, sign, and magnitude are contained in the 48-bit accumulator. Subsequent MAC or MSAC operations
may return the accumulator to a valid 32/40-bit result.
Table 4-3. Summary of S/U, F/I, and R/T Control Bits
S/U
F/I
R/T
Operational Modes
0
0
x
Signed, integer
0
1
0
Signed, fractional
Truncate on MAC.L and MSAC.L
No round on accumulator stores
0
1
1
Signed, fractional
Round on MAC.L and MSAC.L
Round-to-32-bits on accumulator stores
1
0
x
Unsigned, integer
1
1
0
Signed, fractional
Truncate on MAC.L and MSAC.L
Round-to-16-bits on accumulator stores
1
1
1
Signed, fractional
Round on MAC.L and MSAC.L
Round-to-16-bits on accumulator stores
Table 4-2. MACSR Field Descriptions (continued)
Field
Description
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MCF52235CVM60
