MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
7-1
Chapter 7
Clock Module
7.1
Introduction
The clock module allows the MCF52235 to be configured for one of several clocking methods. Clocking
modes include internal phase-locked loop (PLL) clocking with an external clock reference or an external
crystal reference supported by an internal crystal amplifier. The PLL can also be disabled and an external
oscillator can be used to clock the device directly. The device always comes out of reset running in external
crystal mode (although this mode also supports an external clock source) with the PLL disabled. After out
of reset, it is not possible to change the input clock source, although it is possible to enable the PLL and
switch between the PLL clock and the oscillator clock as the source of the system clock.The clock module
contains the following:
•
Crystal amplifier and oscillator (OSC)
•
Phase-locked loop (PLL)
•
Reduced frequency divider (RFD)
•
Status and control registers
•
Control logic
7.2
Features
Features of the clock module include the following:
•
Up to 48 MHz crystal input
•
Provides clock for integrated EPHY
•
On-chip PLL can generate core frequencies up to maximum 60MHz operating frequency
7.3
Modes of Operation
The clock module can be operated in normal PLL mode or external clock mode (PLL disabled).
7.3.1
Normal PLL Mode
In normal PLL mode, the PLL is fully programmable. It can synthesize frequencies ranging from 4x to 18x
the reference frequency and has a post divider capable of reducing this synthesized frequency without
disturbing the PLL. The PLL reference can be a crystal oscillator or an external clock.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
