Clock Module
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
7-6
Freescale Semiconductor
7.7.1.1
Synthesizer Control Register (SYNCR)
IPSBAR
Offset: 0x12_0000 (SYNCR)
Access: Supervisor read/write
15
14
13
12
11
10
9
8
R
LOLRE
MFD2
MFD1
MFD0
LOCRE
RFD2
RFD1
RFD0
W
Reset
0
0
0
1
0
0
0
0
7
6
5
4
3
2
1
0
R
LOCEN
DISCLK
FWKUP
—
—
CLKSRC
1
1
The reset values of PLLEN and CLKSRC are zero, as the PLL is not enabled when the device emerges from
reset).
PLLMODE
PLLEN
1
W
Reset
0
0
0
0
0
0
1
0
Figure 7-3. Synthesizer Control Register (SYNCR)
Table 7-4. SYNCR Field Descriptions
Field
Description
15
LOLRE
Loss-of-lock reset enable. Determines how the system handles a loss-of-lock indication. When operating in
normal mode, the PLL must be locked before setting the LOLRE bit. Otherwise, reset is immediately
asserted. To prevent an immediate reset, the LOLRE bit must be cleared before writing the MFD[2:0] bits
or entering stop mode with the PLL disabled.
0 No reset on loss of lock
1 Reset on loss of lock
Note: In external clock mode, the LOLRE bit has no effect.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
