Clock Module
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
7-9
7.7.1.3
Low Power Control Register (LPCR)
The low power control register (LPCR) controls the low-power divider. It contains a 4-bit field that divides
down the system clock (regardless if the reference clock or PLL clock is driving the system clock) by a
factor of 2
n
(where n is a number from 0 to 15 represented by the 4 bit field). The clock change takes effect
with the next rising edge of the system clock.
4
LOCKS
Sticky indication of PLL lock status.
0 PLL loss of lock since last system reset or MFD change or currently not locked due to exit from STOP
with FWKUP set
1 No unintentional PLL loss of lock since last system reset or MFD change
The lock detect function sets the LOCKS bit when the PLL achieves lock after:
• A system reset
• A write to SYNCR that changes the MFD[2:0] bits
When the PLL loses lock, LOCKS is cleared. When the PLL relocks, LOCKS remains cleared until one of
the two listed events occurs.
In stop mode, if the PLL is intentionally disabled, then the LOCKS bit reflects the value prior to entering stop
mode. However, if FWKUP is set, then LOCKS is cleared until the PLL regains lock. After lock is regained,
the LOCKS bit reflects the value prior to entering stop mode. Furthermore, reading the LOCKS bit at the
same time that the PLL loses lock does not return the current loss of lock condition.
In external clock mode, LOCKS remains cleared after reset. In normal PLL mode, LOCKS is set after reset.
3
LOCK
Set when the PLL is locked. PLL lock occurs when the synthesized frequency is within approximately 0.75%
of the programmed frequency. The PLL loses lock when a frequency deviation of greater than approximately
1.5% occurs. Reading the LOCK flag at the same time that the PLL loses lock or acquires lock does not
return the current condition of the PLL. The power-on reset circuit uses the LOCK bit as a condition for
releasing reset.
If operating in external clock mode, LOCK remains cleared after reset.
0 PLL not locked
1 PLL locked
2
LOCS
Sticky indication of whether a loss-of-clock condition has occurred at any time since exiting reset in normal
PLL mode.
• LOCS equals 0 when the system clocks are operating normally.
• LOCS equals 1 when system clocks have failed due to a reference failure or PLL failure.
After entering stop mode with FWKUP set and the PLL and oscillator intentionally disabled
(STPMD[1:0] = 11), the PLL exits stop mode in the SCM while the oscillator starts up. During this time,
LOCS is temporarily set regardless of LOCEN. It is cleared after the oscillator comes up and the PLL is
attempting to lock.
If a read of the LOCS flag and a loss-of-clock condition occur simultaneously, the flag does not reflect the
current loss-of-clock condition.
A loss-of-clock condition can be detected only if LOCEN equals 1 or the oscillator has not yet returned from
exit from stop mode with FWKUP equaling 1.
0 Loss-of-clock not detected since exiting reset
1 Loss-of-clock detected since exiting reset or oscillator not yet recovered from exit from stop mode with
FWKUP equaling 1
Note: The LOCS flag is always 0 in external clock mode.
1–0
Reserved, should be cleared.
Table 7-5. SYNSR Field Descriptions (continued)
Field
Description
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
