Clock Module
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
7-10
Freescale Semiconductor
7.7.1.4
Clock Control High Register (CCHR)
The CCHR sets the pre-division factor, which divides down the PLL input clock by 1 (CCHR[2:0] = 000)
to 8 (CCHR[2:0] =111). This allows an external oscillator or crystal of more than 10 MHz to be used with
the PLL. The division factor should be set to generate an input clock for the PLL above 1 MHz and below
10 MHz. When CCHR[2:0] are changed or the PLL is disabled in stop mode, the PLL loses lock.
NOTE
The CCHR can be written at any time. However, changes take effect only
after the PLL is disabled and re-enabled.
Figure 7-6. Clock Control High Register (CCHR)
IPSBAR
Offset: 0x12_0007 (LPCR)
Access: Supervisor read/write
7
6
5
4
3
2
1
0
R
—
—
—
—
LPD3
LPD2
LPD1
LPD0
W
Reset:
0
0
0
0
0
0
0
0
Figure 7-5. Low Power Control Register (LPCR)
Table 7-6. LPCR Field Descriptions
Field
Description
7–4
Reserved, should be cleared.
3–0
LPD
Low-power divider factor (divides the system clock by a factor of 2
LPD
).
IPSBAR
Offset: 0x12_0008 (CCHR)
Access: Supervisor read/write
7
6
5
4
3
2
1
0
R
—
—
—
—
—
CCHR2
CCHR1
CCHR0
W
Reset:
0
0
0
0
0
1
0
0
Table 7-7. CCHR Field Descriptions
Field
Description
7–3
Reserved, should be cleared.
2–0
CCHR
Clock control pre-division factor (divides the PLL input clock by a factor of CCHR+1).
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
