Clock Module
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
7-11
7.7.1.5
Real Time Clock Divide Register (RTCDR)
The Real Time Clock Divide Register is a 32 bit read/write register that divides down the oscillator clock
to a 1 Hz clock for the Real Time Clock module. If this register is programmed with zero then the clock to
the Real Time Clock module is disabled, otherwise the oscillator clock is divided by one more than the
value written to the register field (between 2 and 4,294,967,296).
Figure 7-7. Real Time Clock Divide Register (RTCDR)
7.8
Functional Description
This section provides a functional description of the clock module.
7.8.1
Clock Operation During Reset
The PLL is always disabled as the part emerges from Reset, with a default configuration of external crystal
mode (although this mode also supports an external clock source). After out of reset, it is not possible to
change the input clock source, although it is possible to enable the PLL and switch between the PLL clock
and the oscillator clock as the source of the system clock.
IPSBAR
Offset: 0x0011_000C (RTCDR)
Access: Supervisor read/write
31
30
29
28
27
26
25
24
R
RTCDF (31:24)
W
Reset
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
R
RTCDF (23:16)
W
Reset
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
R
RTCDF (15:8)
W
Reset
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
R
RTCDF (7:0)
W
Reset
0
0
0
0
0
0
0
0
Table 7-8. RTCDR Field Descriptions
Field
Description
31–0
RTCDF
Real-time clock divide factor (divides the oscillator clock by a factor of RTCDF+1).
Note: If RTCDF equals 0x0, the clock to the RTC module is disabled.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
