Power Management
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
9-2
Freescale Semiconductor
9.2.1
Peripheral Power Management Registers (PPMRH, PPMRL)
The PPMRH and PPMRL registers provide a bit map for controlling the generation of the module clocks
for each decoded address space associated with the IPS controller. The PPMR
x
provides a unique control
bit for each of these address spaces that defines whether the module clock for the given space is enabled
or disabled.
NOTE
It is software’s responsibility to appropriately disable module clocks using
the PPMR
x
only when a module is completely unused or quiescent.
Because the operation of the IPS controller and the system control module (SCM) are fundamental to the
operation of the system, the clocks for these three modules cannot be disabled.
The individual bits of the PPMR
x
can be modified using a read-modify-write to this register directly or
indirectly through writes to the PPMRS and PPMRC registers to set/clear individual bits.
for the PPMRH definition.
IPSBAR
Offset:
0x00_000C (PPMRH)
Access: read/write
31
30
29
28
27
26
25
24
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
R
0
0
CDRNGA
CDEPHY
CDCFM
CDFCAN
CDPWM
CDGPT
W
Reset
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
R
CDADC
0
0
CDPIT1
CDPIT0
0
CDEPORT
CDPORTS
W
Reset
0
0
0
0
0
0
0
0
Figure 9-1. Peripheral Power Management Register High (PPMRH)
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
