Chip Configuration Module (CCM)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
12-4
Freescale Semiconductor
12.3.3.2
Reset Configuration Register (RCON)
At reset, RCON determines the default operation of certain chip functions. All default functions defined
by the RCON values can only be overridden during reset configuration (see
”) if the external RCON pin is asserted. RCON is a read-only register.
Table 12-4. CCR Field Descriptions
Field
Description
1–
—
Reserved, should be cleared.
6
SZEN
TSIZ[1:0] enable. This read/write bit enables the TSIZ[1:0] function of the external pins.
0 TSIZ[1:0] function disabled.
1 TSIZ[1:0] function enabled.
5
PSTEN
PST[3:0]/DDATA[3:0] enable. This read/write bit enables the Processor Status (PST) and Debug Data (DDATA)
functions of the external pins.
0 PST/DDATA function disabled.
1 PST/DDATA function enabled.
4
—
Reserved, should be cleared.
3
BME
Bus monitor enable. This read/write bit enables the bus monitor to operate during external bus cycles.
0 Bus monitor disabled for external bus cycles.
1 Bus monitor enabled for external bus cycles.
shows the read/write accessibility of this write-once bit.
2–0
BMT
Bus monitor timing. This field selects the timeout period (in system clocks) for the bus monitor.
000 65536
001 32768
010 16384
011 8192
100 4096
101 2048
110 1024
111 512
shows the read/write accessibility of this write-once bit.
IPSBAR
Offset:
0x11_0008 (RCON)
Access: Supervisor read-only
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
RLOAD
0
0
0
0
MODE
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 12-3. Reset Configuration Register (RCON)
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
