MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
15-1
Chapter 15
Interrupt Controller Module
This section details the functionality for the interrupt controller. The general features of the interrupt
controller include:
•
Interrupt sources
— 119 fully-programmable interrupt sources (of which some are reserved)
— 7 fixed-level interrupt sources
•
Each of the sources has a unique interrupt control register (ICR
nx
) to define the software-assigned
levels and priorities within the level
•
Unique vector number for each interrupt source
•
Ability to mask any individual interrupt source, plus global mask-all capability
•
Supports hardware and software interrupt acknowledge cycles
•
Wake-up signal from low-power stop modes
The 50 fully-programmable and seven fixed-level interrupt sources for the interrupt controller manage the
complete set of interrupt sources from all of the modules on the device. This section describes how the
interrupt sources are mapped to the interrupt controller logic and how interrupts are serviced.
15.1
68K/ColdFire Interrupt Architecture Overview
Before continuing with the specifics of the interrupt controller, a brief review of the interrupt architecture
of the 68K/ColdFire family is appropriate.
The interrupt architecture of ColdFire is exactly the same as the M68000 family, where there is a 3-bit
encoded interrupt priority level sent from the interrupt controller to the core, providing 7 levels of interrupt
requests. Level 7 represents the highest priority interrupt level, while level 1 is the lowest priority. The
processor samples for active interrupt requests once per instruction by comparing the encoded priority
level against a 3-bit interrupt mask value (I) contained in bits 10:8 of the core’s status register (SR). If the
priority level is greater than the SR[I] field at the sample point, the processor suspends normal instruction
execution and initiates interrupt exception processing. Level 7 interrupts are treated as non-maskable and
edge-sensitive within the processor, while levels 1–6 are treated as level-sensitive and may be masked
depending on the value of the SR[I] field. For correct operation, ColdFire requires that the interrupt source,
after asserted, remains asserted until explicitly disabled by the interrupt service routine.
During the interrupt exception processing, the CPU enters supervisor mode, disables trace mode, and then
fetches an 8-bit vector from the interrupt controller. This byte-sized operand fetch is known as the interrupt
acknowledge (IACK) cycle, with the ColdFire implementation using a special encoding of the transfer
type and transfer modifier attributes to distinguish this data fetch from a normal memory access. The
fetched data provides an index into the exception vector table, which contains 256 addresses, each pointing
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MCF52235CVM60
