Ethernet Physical Transceiver (EPHY)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
19-24
Freescale Semiconductor
Figure 19-19. EPHY Start-Up Delay
If the auto-negotiation mode of operation is desired, the ANDIS bit in the EPHYCTL0 must be set to 0
and the DIS100 and DIS10 bits must be cleared prior to setting EPHYEN to 1. Refer to
for more information on auto-negotiation operation.
If the mode of operation is set manually, the ANDIS bit must be set to 1 in the EPHYCTL0 register and
the DIS100 and DIS10 bits must be cleared prior to setting EPHYEN to 1. After the EPHYEN bit has been
set and the start-up delay period is completed, the mode of operation can be configured through the MII
registers.
summarizes the MII register configuration and operational modes.
Table 19-18. Operational Configuration While Auto-Negotiation is Disabled
1
1
Symbol mode is not supported.
Bit 0.12
Auto
Neg.
Bit 0.13
Data
Rate
Bit 0.8
Duplex
Bit 18.6
Encoder
Bypass
Bit 18.5
Scrambler
Bypass
Bit 18.7
Symbol
Unalign
Operation
0
0
1
X
X
X
10BASE-T full-duplex
0
0
0
X
X
X
10BASE-T half-duplex
0
1
1
0
0
0
100BASE-TX full-duplex
0
1
1
1
0
0
100BASE-TX full-duplex with encoder
bypass (symbol mode) — aligned
0
1
1
1
0
1
100BASE-TX full-duplex with encoder
bypass (symbol mode) — unaligned
0
1
1
1
1
0
100BASE-TX full-duplex with scrambler
and encoder bypassed (symbol mode),
aligned
0
1
1
1
1
1
100BASE-TX full-duplex with scrambler
and encoder bypassed (symbol mode),
unaligned
0
1
0
0
0
0
100BASE-TX half-duplex
EPHYEN
tStart-up
MDIO
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
