DMA Controller Module
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
20-7
When a transfer sequence is initiated and BCR
n
[BCR] is not a multiple of 16, 4, or 2 when the DMA is
configured for line, longword, or word transfers, respectively, DSR
n
[CE] is set and no transfer occurs.
IPSBAR
Offsets:
0x00_0108 (DSR0)
0x00_0118 (DSR1)
0x00_0128 (DSR2)
0x00_0138 (DSR3)
Access: Read/write
7
6
5
4
3
2
1
0
R
0
CE
BES
BED
0
REQ
BSY
DONE
W
Reset:
0
0
0
0
0
0
0
0
Figure 20-7. DMA Status Registers (DSRn)
Table 20-3. DSRn Field Descriptions
Field
Description
7
Reserved, should be cleared.
6
CE
Configuration error. Occurs when BCR, SAR, or DAR does not match the requested transfer size, or if
BCR equals 0 when the DMA receives a start condition. CE is cleared at hardware reset or by writing a 1 to
DSR[DONE].
0 No configuration error exists.
1 A configuration error has occurred.
5
BES
Bus error on source
0 No bus error occurred.
1 The DMA channel terminated with a bus error during the read portion of a transfer.
4
BED
Bus error on destination
0 No bus error occurred.
1 The DMA channel terminated with a bus error during the write portion of a transfer.
3
Reserved, should be cleared.
2
REQ
Request
0 No request is pending or the channel is currently active. Cleared when the channel is selected.
1 The DMA channel has a transfer remaining and the channel is not selected.
1
BSY
Busy
0 DMA channel is inactive. Cleared when the DMA has finished the last transaction.
1 BSY is set the first time the channel is enabled after a transfer is initiated.
0
DONE
Transactions done. Set when all DMA controller transactions complete, as determined by transfer count or error
conditions. When BCR reaches zero, DONE is set when the final transfer completes successfully. DONE can also
be used to abort a transfer by resetting the status bits. When a transfer completes, software must clear DONE
before reprogramming the DMA.
0 Writing or reading a 0 has no effect.
1 DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and can be used in an interrupt
handler to clear the DMA interrupt and error bits.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
