Programmable Interrupt Timers (PIT0–PIT1)
Freescale Semiconductor
22-4
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
22.2.2
PIT Modulus Register (PMRn)
The 16-bit read/write PMR
n
contains the timer modulus value loaded into the PIT counter when the count
reaches 0x0000 and the PCSR
n
[RLD] bit is set.
When the PCSR
n
[OVW] bit is set, PMR
n
is transparent, and the value written to PMR
n
is immediately
loaded into the PIT counter. The prescaler counter is reset (0xFFFF) anytime a new value is loaded into
the PIT counter and also during reset. Reading the PMR
n
returns the value written in the modulus latch.
Reset initializes PMR
n
to 0xFFFF.
5
DBG
Debug mode bit. Controls the function of PIT in halted/debug mode. Reset clears DBG. During debug mode, register
read and write accesses function normally. When debug mode is exited, timer operation continues from the state it
was in before entering debug mode, but any updates made in debug mode remain.
0 PIT function not affected in debug mode
1 PIT function stopped in debug mode
Note: Changing the DBG bit from 1 to 0 during debug mode starts the PIT timer. Likewise, changing the DBG bit
from 0 to 1 during debug mode stops the PIT timer.
4
OVW
Overwrite. Enables writing to PMRn to immediately overwrite the value in the PIT counter.
0 Value in PMRn replaces value in PIT counter when count reaches 0x0000.
1 Writing PMRn immediately replaces value in PIT counter.
3
PIE
PIT interrupt enable. This read/write bit enables PIF flag to generate interrupt requests.
0 PIF interrupt requests disabled
1 PIF interrupt requests enabled
2
PIF
PIT interrupt flag. This read/write bit is set when PIT counter reaches 0x0000. Clear PIF by writing a 1 to it or by
writing to PMR. Writing 0 has no effect. Reset clears PIF.
0 PIT count has not reached 0x0000.
1 PIT count has reached 0x0000.
1
RLD
Reload bit. The read/write reload bit enables loading the value of PMRn into PIT counter when the count reaches
0x0000.
0 Counter rolls over to 0xFFFF on count of 0x0000
1 Counter reloaded from PMRn on count of 0x0000
0
EN
PIT enable bit. Enables PIT operation. When PIT is disabled, counter and prescaler are held in a stopped state. This
bit is read anytime, write anytime.
0 PIT disabled
1 PIT enabled
IPSBAR
Offset:
0x15_0002 (PMR0)
0x16_0002 (PMR
1
)
Access: Supervisor
read/write
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
PM
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 22-3. PIT Modulus Register (PMRn)
Table 22-3. PCSRn Field Descriptions (continued)
Field
Description
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
