General Purpose Timer Module (GPT)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
23-7
23.6.4
GPT Output Compare 3 Data Register (GPTOC3D)
NOTE
A successful channel 3 output compare overrides any channel 2:0 compares.
For each OC3M bit that is set, the output compare action reflects the
corresponding OC3D bit.
23.6.5
GPT Counter Register (GPTCNT)
IPSBAR
Offset: 0x1A_0003 (GPTOC3D)
Access: Supervisor read/write
7
6
5
4
3
2
1
0
R
0
0
0
0
OC3D
W
Reset:
0
0
0
0
0
0
0
0
Figure 23-5. GPT Output Compare 3 Data Register (GPTOC3D)
Table 23-7. GPTOC3D Field Descriptions
Field
Description
7–4
Reserved, should be cleared.
3–0
OC3D
Output compare 3 data. When a successful channel 3 output compare occurs, these bits transfer to the PORTTn
data register if the corresponding OC3Mn bits are set. These bits are read anytime, write anytime.
IPSBAR
Offset: 0x1A_0004 (GPTCNT)
Access: Supervisor read-only
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
CNTR
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 23-6. GPT Counter Register (GPTCNT)
Table 23-8. GPTCNT Field Descriptions
Field
Description
15–0
CNTR
Read-only field that provides the current count of the timer counter. To ensure coherent reading of the timer counter,
such that a timer rollover does not occur between two back-to-back 8-bit reads, it is recommended that only word
(16-bit) accesses be used.
A write to GPTCNT may have an extra cycle on the first count because the write is not synchronized with the
prescaler clock. The write occurs at least one cycle before the synchronization of the prescaler clock.
These bits are read anytime. They should be written to only in test (special) mode; writing to them has no effect in
normal modes.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
