General Purpose Timer Module (GPT)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
23-10
Freescale Semiconductor
23.6.9
GPT Control Register 2 (GPTCTL2)
23.6.10 GPT Interrupt Enable Register (GPTIE)
IPSBAR
Offset: 0x1A_000B (GPTCTL2)
Access: Supervisor read/write
7
6
5
4
3
2
1
0
R
EDG3B
EDG3A
EDG2B
EDG2A
EDG1B
EDG1A
EDG0B
EDG0A
W
Reset:
0
0
0
0
0
0
0
0
Figure 23-11. GPT Control Register 2(GPTCTL2)
Table 23-12. GPTLCTL2 Field Descriptions
Field
Description
7–0
EDGn[B:A]
Input capture edge control. Configures the input capture edge detector circuits for each channel. These bits are
read anytime, write anytime.
00 Input capture disabled
01 Input capture on rising edges only
10 Input capture on falling edges only
11 Input capture on any edge (rising or falling)
IPSBAR
Offset: 0x1A_000C (GPTIE)
Access: Supervisor read/write
7
6
5
4
3
2
1
0
R
0
0
0
0
CI
W
Reset:
0
0
0
0
0
0
0
0
Figure 23-12. GPT Interrupt Enable Register (GPTIE)
Table 23-13. GPTIE Field Descriptions
Field
Description
7–4
Reserved, should be cleared.
3–0
Cnl
Channel interrupt enable. Enables the C[3:0]F flags in GPT flag register 1 to generate interrupt requests for each
channel. These bits are read anytime, write anytime.
1 Corresponding channel interrupt requests enabled
0 Corresponding channel interrupt requests disabled
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
