General Purpose Timer Module (GPT)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
23-16
Freescale Semiconductor
23.6.18 GPT Port Data Register (GPTPORT)
23.6.19 GPT Port Data Direction Register (GPTDDR)
IPSBAR
Offset: 0x1A_001D (GPTPORT)
Access: Supervisor read/write
7
6
5
4
3
2
1
0
R
0
0
0
0
PORTT
W
Reset:
0
0
0
0
0
0
0
0
Figure 23-20. GPT Port Data Register (GPTPORT)
Table 23-21. GPTPORT Field Descriptions
Field
Description
7–4
Reserved, should be cleared.
3–0
PORTT
GPT port input capture/output compare data. Data written to GPTPORT is buffered and drives the pins only when
they are configured as general-purpose outputs.
Reading an input (DDR bit = 0) reads the pin state; reading an output (DDR bit = 1) reads the latched value. Writing
to a pin configured as a GPT output does not change the pin state. These bits are read anytime (read pin state when
corresponding PORTTn bit is 0, read pin driver state when corresponding GPTDDR bit is 1), write anytime.
7
6
5
4
3
0
Field
—
DDRT
GPT Function
—
IC/OC
Pulse Accumulator Function
—
PAI
—
Reset
0000_0000
R/W
R/W
Address
0x1A_001E
Figure 23-21. GPT Port Data Direction Register (GPTDDR)
Table 23-22. GPTDDR Field Descriptions
Bit(s)
Name
Description
7–4
—
Reserved, should be cleared.
3–0
DDRT
Control the port logic of PORTTn. Reset clears the PORTTn data direction register,
configuring all GPT port pins as inputs. These bits are read anytime, write anytime.
1 Corresponding pin configured as output
0 Corresponding pin configured as input
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
