DMA Timers (DTIM0–DTIM3)
Freescale Semiconductor
24-5
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
24.2.2
DMA Timer Extended Mode Registers (DTXMRn)
The DTXMR
n
registers program DMA request and increment modes for the timers.
24.2.3
DMA Timer Event Registers (DTERn)
DTER
n
, shown in
, reports capture or reference events by setting DTER
n
[CAP] or
DTER
n
[REF]. This reporting happens regardless of the corresponding DMA request or interrupt enable
values, DTXMR
n
[DMAEN] and DTMR
n
[ORRI,CE].
Writing a 1 to DTER
n
[REF] or DTER
n
[CAP] clears it (writing a 0 does not affect bit value); both bits can
be cleared at the same time. If configured to generate an interrupt request, clear REF and CAP early in the
interrupt service routine so the timer module can negate the interrupt request signal to the interrupt
controller. If configured to generate a DMA request, processing of the DMA data transfer automatically
clears the REF and CAP flags via the internal DMA ACK signal.
IPSBAR
Offset:
0x00_0402 (DTXMR0)
0x00_0442 (DTXMR1)
0x00_0482 (DTXMR2)
0x00_04C2 (DTXMR3)
Access: User read/write
7
6
5
4
3
2
1
0
R
DMAEN
HALTED
0
0
0
0
0
MODE16
W
Reset:
0
0
0
0
0
0
0
0
Figure 24-3. DTXMRn Registers
Table 24-3. DTXMRn Field Descriptions
Field
Description
7
DMAEN
DMA request. Enables DMA request output on counter reference match or capture edge event.
0 DMA request disabled
1 DMA request enabled
6
HALTED
Controls the counter when the core is halted. This allows debug mode to be entered without timer interrupts affecting
the debug flow.
0 Timer function is not affected by core halt.
1 Timer stops counting while the core is halted.
Note: This bit is only applicable in reference compare mode, see
Section 24.3.3, “Reference Compare.”
5–1
Reserved, must be cleared.
0
MODE16
Selects the increment mode for the timer. Setting MODE16 is intended to exercise the upper bits of the 32-bit timer
in diagnostic software without requiring the timer to count through its entire dynamic range. When set, the counter’s
upper 16 bits mirror its lower 16 bits. All 32 bits of the counter remain compared to the reference value.
0 Increment timer by 1
1 Increment timer by 65,537
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
