DMA Timers (DTIM0–DTIM3)
Freescale Semiconductor
24-9
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
If the free run/restart bit (DTMR
n
[FRR]) is set, a new count starts. If it is clear, the timer keeps running.
24.3.4
Output Mode
When a timer reaches the reference value selected by DTRR, it can send an output signal on DTOUT
n
.
DTOUT
n
can be an active-low pulse or a toggle of the current output, as selected by the DTMR
n
[OM] bit.
24.4
Initialization/Application Information
The general-purpose timer modules typically, but not necessarily, follow this program order:
•
The DTMR
n
and DTXMR
n
registers are configured for the desired function and behavior.
— Count and compare to a reference value stored in the DTRR
n
register
— Capture the timer value on an edge detected on DTIN
n
— Configure DTOUT
n
output mode
— Increment counter by 1 or by 65,537 (16-bit mode)
— Enable/disable interrupt or DMA request on counter reference match or capture edge
•
The DTMR
n
[CLK] register is configured to select the clock source to be routed to the prescaler.
— Internal bus clock (can be divided by 1 or 16)
— DTIN
n
, the maximum value of DTIN
n
is 1/5 of the internal bus clock, as described in the
device’s electrical characteristics
NOTE
DTIN
n
may not be configured as a clock source when the timer capture
mode is selected or indeterminate operation results.
•
The 8-bit DTMR
n
[PS] prescaler value is set.
•
Using DTMR
n
[RST], counter is cleared and started.
•
Timer events are managed with an interrupt service routine, a DMA request, or by a software
polling mechanism.
24.4.1
Code Example
The following code provides an example of how to initialize and use DMA Timer0 for counting time-out
periods.
DTMR0 EQU 0x400 ;Timer0 mode register
DTMR1 EQU 0x440 ;Timer1 mode register
DTRR0 EQU 0x404 ;Timer0 reference register
DTRR1 EQU 0x444 ;Timer1 reference register
DTCR0 EQU 0x408 ;Timer0 capture register
DTCR1 EQU 0x448 ;Timer1 capture register
DTCN0 EQU 0x40C ;Timer0 counter register
DTCN1 EQU 0x44C ;Timer1 counter register
DTER0 EQU 0x403 ;Timer0 event register
DTER1 EQU 0x443 ;Timer1 event register
* TMR0 is defined as: *
*[PS] = 0xFF,
divide clock by 256
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MCF52235CVM60
