Queued Serial Peripheral Interface (QSPI)
25-7
Freescale Semiconductor
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
25.3.5
QSPI Address Register (QAR)
The QAR is used to specify the location in the QSPI RAM that read and write operations affect. As shown
in
, the transmit RAM is located at addresses 0x0 to 0xF, the receive RAM
is located at 0x10 to 0x1F, and the command RAM is located at 0x20 to 0x2F. (These addresses refer to
the QSPI RAM space, not the device memory map.)
NOTE
A read or write to the QSPI RAM causes QAR to increment. However, the
QAR does not wrap after the last queue entry within each section of the
RAM. The application software must manage address range errors.
Table 25-6. QIR Field Descriptions
Field
Description
15
WCEFB
Write collision access error enable. A write collision occurs during a data transfer when the RAM entry containing
the current command is written to by the CPU with the QDR. When this bit is asserted, the write access to QDR
results in an access error.
14
ABRTB
Abort access error enable. An abort occurs when QDLYR[SPE] is cleared during a transfer. When set, an attempt to
clear QDLYR[SPE] during a transfer results in an access error.
13
Reserved, must be cleared.
12
ABRTL
Abort lock-out. When set, QDLYR[SPE] cannot be cleared by writing to the QDLYR. QDLYR[SPE] is only cleared by
the QSPI when a transfer completes.
11
WCEFE
Write collision (WCEF) interrupt enable.
0 Write collision interrupt disabled
1 Write collision interrupt enabled
10
ABRTE
Abort (ABRT) interrupt enable.
0 Abort interrupt disabled
1 Abort interrupt enabled
9
Reserved, must be cleared.
8
SPIFE
QSPI finished (SPIF) interrupt enable.
0 SPIF interrupt disabled
1 SPIF interrupt enabled
7–4
Reserved, must be cleared.
3
WCEF
Write collision error flag. Indicates that an attempt has been made to write to the RAM entry that is currently being
executed. Writing a 1 to this bit (w1c) clears it and writing 0 has no effect.
2
ABRT
Abort flag. Indicates that QDLYR[SPE] has been cleared by the user writing to the QDLYR rather than by completion
of the command queue by the QSPI. Writing a 1 to this bit (w1c) clears it and writing 0 has no effect.
1
Reserved, must be cleared.
0
SPIF
QSPI finished flag. Asserted when the QSPI has completed all the commands in the queue. Set on completion of
the command pointed to by QWR[ENDQP], and on completion of the current command after assertion of
QWR[HALT]. In wraparound mode, this bit is set every time the command pointed to by QWR[ENDQP] is completed.
Writing a 1 to this bit (w1c) clears it and writing 0 has no effect.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
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currently
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for
import
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sale
in
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States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
