UART Modules
Freescale Semiconductor
26-27
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
3. Unmask appropriate bits in the core’s status register (SR) to enable interrupts.
4. If TXRDY or RXRDY generates interrupt requests, verify that DMAREQC (in the SCM) does not
also assign the UART’s TXRDY and RXRDY into DMA channels.
5. Initialize interrupts in the UART, see
.
26.5.1.2
Setting up the UART to Request DMA Service
The UART is capable of generating two internal DMA request signals: transmit and receive.
The transmit DMA request signal is asserted when the TXRDY (transmitter ready) in the UART interrupt
status register (UISR
n
[TXRDY]) is set. When the transmit DMA request signal is asserted, the DMA can
initiate a data copy, reading the next character transmitted from memory and writing it into the UART
transmit buffer (UTB
n
). This allows the DMA channel to stream data from memory to the UART for
transmission without processor intervention. After the entire message has been moved into the UART, the
DMA would typically generate an end-of-data-transfer interrupt request to the CPU. The resulting
interrupt service routine (ISR) could query the UART programming model to determine the
end-of-transmission status.
Similarly, the receive DMA request signal is asserted when the FIFO full or receive ready
(FFULL/RXRDY) flag in the interrupt status register (UISR
n
[FFULL/RXRDY]) is set. When the receive
DMA request signal is asserted, the DMA can initiate a data move, reading the appropriate characters from
the UART receive buffer (URB
n
) and storing them in memory. This allows the DMA channel to stream
data from the UART receive buffer into memory without processor intervention. After the entire message
has been moved from the UART, the DMA would typically generate an end-of-data-transfer interrupt
request to the CPU. The resulting interrupt service routine (ISR) should query the UART programming
model to determine the end-of-transmission status. In typical applications, the receive DMA request
should be configured to use RXRDY directly (and not FFULL) to remove any complications related to
retrieving the final characters from the FIFO buffer.
The implementation described in this section allows independent DMA processing of transmit and receive
data while continuing to support interrupt notification to the processor for CTS change-of-state and delta
break error managing.
Table 26-13. UART Interrupts
Register
Bit
Interrupt
UMR1n
6
RxIRQ
UIMRn
7
Change of State (COS)
UIMRn
2
Delta Break
UIMRn
1
RxFIFO Full
UIMRn
0
TXRDY
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MCF52235CVM60
