I
2
C Interface
Freescale Semiconductor
27-3
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
27.2
Memory Map/Register Definition
The below table lists the configuration registers used in the I
2
C interface.
27.2.1
I
2
C Address Register (I2ADR)
I2ADR holds the address the I
2
C responds to when addressed as a slave. It is not the address sent on the
bus during the address transfer when the module is performing a master transfer.
27.2.2
I
2
C Frequency Divider Register (I2FDR)
, provides a programmable prescaler to configure the I
2
C clock for
bit-rate selection.
Table 27-1. I
2
C Module Memory Map
IPSBAR
Offset
Register
Access
Reset Value
Section/Page
0x00_0300
I
2
C Address Register (I2ADR)
R/W
0x00
0x00_0304
I
2
C Frequency Divider Register (I2FDR)
R/W
0x00
0x00_0308
I
2
C Control Register (I2CR)
R/W
0x00
0x00_030C
I
2
C Status Register (I2SR)
R/W
0x81
0x00_0310
I
2
C Data I/O Register (I2DR)
R/W
0x00
IPSBAR
Offset:
0x00_0300 (I2ADR)
Access: User read/write
7
6
5
4
3
2
1
0
R
ADR
0
W
Reset:
0
0
0
0
0
0
0
0
Figure 27-2. I
2
C Address Register (I2ADR)
Table 27-2. I2ADR Field Descriptions
Field
Description
7–1
ADR
Slave address. Contains the specific slave address to be used by the I
2
C module. Slave mode is the default I
2
C mode
for an address match on the bus.
0
Reserved, must be cleared.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
