I
2
C Interface
27-6
Freescale Semiconductor
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
27.2.4
I
2
C Status Register (I2SR)
I2SR contains bits that indicate transaction direction and status.
IPSBAR
Offset:
0x00_030C (I2SR)
Access: User read/write
7
6
5
4
3
2
1
0
R
ICF
IAAS
IBB
IAL
0
SRW
IIF
RXAK
W
Reset:
1
0
0
0
0
0
0
1
Figure 27-5. I
2
C Status Register (I2SR)
Table 27-5. I2SR Field Descriptions
Field
Description
7
ICF
I
2
C Data transferring bit. While one byte of data is transferred, ICF is cleared.
0 Transfer in progress
1 Transfer complete. Set by falling edge of ninth clock of a byte transfer.
6
IAAS
I
2
C addressed as a slave bit. The CPU is interrupted if I2CR[IIEN] is set. Next, the CPU must check SRW and set
its TX/RX mode accordingly. Writing to I2CR clears this bit.
0 Not addressed.
1 Addressed as a slave. Set when its own address (IADR) matches the calling address.
5
IBB
I
2
C bus busy bit. Indicates the status of the bus.
0 Bus is idle. If a STOP signal is detected, IBB is cleared.
1 Bus is busy. When START is detected, IBB is set.
4
IAL
I
2
C arbitration lost. Set by hardware in the following circumstances. (IAL must be cleared by software by writing zero
to it.)
• I2C_SDA sampled low when the master drives high during an address or data-transmit cycle.
• I2C_SDA sampled low when the master drives high during the acknowledge bit of a data-receive cycle.
• A start cycle is attempted when the bus is busy.
• A repeated start cycle is requested in slave mode.
• A stop condition is detected when the master did not request it.
3
Reserved, must be cleared.
2
SRW
Slave read/write. When IAAS is set, SRW indicates the value of the R/W command bit of the calling address sent
from the master. SRW is valid only when a complete transfer has occurred, no other transfers have been initiated,
and the I
2
C module is a slave and has an address match.
0 Slave receive, master writing to slave.
1 Slave transmit, master reading from slave.
1
IIF
I
2
C interrupt. Must be cleared by software by writing a 0 in the interrupt routine.
0 No I
2
C interrupt pending
1 An interrupt is pending, which causes a processor interrupt request (if IIEN = 1). Set when one of the following
occurs:
• Complete one byte transfer (set at the falling edge of the ninth clock)
• Reception of a calling address that matches its own specific address in slave-receive mode
• Arbitration lost
0
RXAK
Received acknowledge. The value of I2C_SDA during the acknowledge bit of a bus cycle.
0 An acknowledge signal was received after the completion of 8-bit data transmission on the bus
1 No acknowledge signal was detected at the ninth clock.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
