Analog-to-Digital Converter (ADC)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
28-21
Freescale Semiconductor
28.5
Functional Description
The ADC’s conversion process is initiated by a sync signal from one of two input pins (SYNCx) or by
writing 1 to a START
n
bit.
Starting a single conversion actually begins a sequence of conversions, or a scan of up to 8 single-ended
or differential samples one at a time in sequential scan mode. The operation of the module in sequential
scan mode is shown in
Figure 28-18. Sequential Mode Operation of the ADC
Scan sequence is determined by defining eight sample slots in ADLST1/2 registers, processed in order
SAMPLE0-7 during sequential scan or in order SAMPLE0-3 by converter A and in order SAMPLE4-7 by
converter B in parallel scan. SAMPLE slots may be disabled using the SDIS register.
The following pairs of analog inputs can be configured as a differential pair: AN0-1, AN2-3, AN4-5, and
AN6-7. When configured as a differential pair, a reference to either member of the differential pair by a
sample slot results in a differential measurement using that differential pair.
AN3
AN2
AN1
AN0
V+
V
REFL
Channel Select
V–
ADCA
12
Single-Ended vs
Crossbars allow AN0-3
to be stored in samples 4-7,
or AN4-7 to be stored in
samples 0-3
Differential
12
+
ADOFS[0:3]
13
Zero Crossing Logic
+
–
ADHLMT[4:7]
>
ADRSLT[0:3]
Zero Crossing
or Error Limit
Interrupt
ADLLMT[4:7]
<
12
12
+
ADOFS[4:7]
13
Zero Crossing Logic
+
–
ADRSLT[4:7]
12
AN7
AN6
AN5
AN4
V+
V
REFL
Channel Select
V–
ADCB
Single-Ended vs
Differential
12
ADHLMT[0:3]
>
ADLLMT[0:3]
<
Test Data
(From CPU)
Test Data
(From CPU)
ADC2
ADC1
ADC0
End of
Scan B
Interrupt
End of
Scan A
Interrupt
IRQ Logic
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
